A Full Duplex LoRaWAN® Gateway for the U.S. 915MHz ISM Band

The LoRa® Corecell Full-Duplex gateway reference design is a highly integrated indoor and outdoor gateway solution designed specifically for the U.S.s 915MHz ISM band. This full-duplex gateway design makes it possible to expand network capacity for outdoor and indoor applications, such as smart metering, smart offices, smart buildings, and smart factories. Moreover, it increases the capacity of networks with fewer gateways, thus providing cost savings for end customers when compared to cellular charges.

Unlike typical half-duplex designs, a full-duplex gateway allows simultaneous transmission and reception of LoRa packets. This drastically reduces latency by eliminating the need for uplink traffic to be gated by downlink traffic, and vice versa. For example, it improves the response time of LoRaWAN® protocol messages for applications that require fast acknowledgement from the gateway, such as performing Firmware Updates Over-The-Air (FUOTA) while processing uplink traffic. It also reduces the time and cost of managing end devices.

Figure 1. Block Diagram of the SX1302 LoRa® Corecell Full-Duplex Gateway Reference Design

Key Features and Benefits

• Supports Full Duplex Operation
  • 8-Channel Uplink and 1 Channel Downlink
• Operates in the U.S. 915MHz ISM Band
• Provides all of the advanced capabilities of the LoRa Core ™ SX1302
  • 64x LoRa packet detectors
  • 16x 125kHz LoRa demodulators for SF5 to SF12 and SF5 to SF10
  • 1x 125/250/500kHz Single SF LoRa demodulator
  • 1x (G)FSK demodulator
  • 10x power reduction compared to the previous generation of LoRa baseband
• Transmit output at antenna up to +27dBm
• Receive sensitivity at antenna down to -140.8dBm at SF12, 125kHz BW

Detailed Description

From a hardware perspective, the LoRa® Corecell Reference Design for Full Duplex Gateway Applications (hereafter LoRa Corecell Full Duplexer Gateway) consists of three major blocks: LoRa Corecell board, duplexer, and Raspberry Pi.

Based on the SX1302 and SX1257 platforms, the LoRa Corecell board is designed to simultaneously support 8 uplink channels and one downlink channel (Figure 2). Thanks to the advanced design of the SX1302 baseband IC, the uplink channels can detect up to 64 different LoRa packets and simultaneously demodulate 16 125kHz LoRa packets with spreading factors between SF5 and SF12. It is also equipped with one 125/250/500kHz demodulator for single SF operation, and one (G)FSK demodulator for legacy applications. In addition to its demodulation capability, the SX1302 also offers significant power consumption and cost reduction when compared to the previous generation of LoRa baseband ICs.

In addition to the external duplexer, the SX1257 is the other major enabler for the full-duplex capability of this reference design. The SX1257 is a highly integrated RF transceiver that is equipped with two independent synthesizers; thus enabling the receiver and transmitter to be tuned to two different frequencies. Each SX1257 is tuned to capture 1MHz (on up to five channels) of the RF spectrum, with uplink frequencies ranging from 902.3MHz to 914.9MHz and downlink channels from 923MHz to 928MHz.

And, with the help of a discrete high performance power amplifier and low noise amplifier, the output power at the antenna port can be as high as +27dBm, and the receive sensitivity can be as low as -140.8dBm.

Figure 2: SX1302 and SX1257 Corecell Board

The primary function of the duplexer on this reference design is to isolate/protect the sensitive receiver front end from being desensitized by the much more powerful signal that is being broadcast by the transmitter. There are many types of duplexers available out in the market, such as cavity, ceramic, surface acoustic wave (SAW), etc. Cavity duplexers are generally larger in size and higher in cost, but probably offer the best performance. Ceramic duplexers are usually much less expensive, with acceptable performance, but are usually still fairly large. Lastly, SAW duplexers are the smallest and probably the least expensive. However, their power handling capability and performance are generally at the lowest level. As an effort to maintain flexibility, we’ve intentionally kept the duplexer board separate from the LoRa Corecell board. For outdoor applications, the cavity duplexer was chosen for its performance capabilities. For indoor applications, where cost is generally outweighs performance, a ceramic duplexer was chosen.

Figure 3. Complete reference design with cavity duplexer

Figure 4. Complete reference design with ceramic duplexer

Table 1. Duplexer Specifications

Performance Summary

Following are the performance data of the LoRa Corecell Full Duplexer Gateway using the cavity duplexer as shown in Figure 3.

All of the transmit measurements were done at P_OUT at Antenna = +27dBm, bandwidth = 500kHz, and 25 degrees Celsius, unless otherwise stated.

Table 2. Transmitter Modulation Bandwidth

The results shown in Table 2 comply with the Federal Communications Commission (FCC) requirement (Chapter 15.247(a)(2)) that 6dB bandwidth of the transmitted signal shall be at least 500kHz for supported spreading factors, SF7-SF12.

Table 3. Margin in Out-of-Band Emissions in the Non-Restricted Band (927.5MHz)

The results shown in Table 3 illustrate the out-of-band emissions in the non-restricted band are greater than 30dB below the reference emission level, and hence comply with the specified requirements in paragraph 15.247(d) of the FCC regulations.

Chapter 15.247(e) of the FCC regulations requires that the power spectral density shall not be greater than +8dBm in any 3kHz band during any time interval of continuous transmission.

Table 4. Maximum Transmit Power Spectral Density

The results shown in Table 4 illustrate that the maximum power spectral density complies with the +8dBm/3kHz limit as specified by the FCC regulations.

Table 5. Margin in Spurious Emissions for SF7-SF12

The results shown in Table 5 illustrate compliance with the spurious emissions limits as specified in paragraphs 15.209(a) for restricted emission limits specified, and in 15.247(d) for non-restricted limits specified in the FCC regulations

All sensitivity measurements are based on Radio 0, carrier frequency = 908.5MHz, bandwidth = 125kHz, PER = 10 percent, and temperature = 25 degrees Celsius, unless otherwise stated.

Table 6. Sensitivity vs SF

Table 7. Sensitivity Level vs Multi SF Channel (SF7)

Table 8. Sensitivity Level vs Single SF Channel (SF8)

Software/Firmware Packages

The HAL and packet forwarder for this reference design can be found at:

https://github.com/Lora-net/sx1302_hal/tree/master-fdd-us915

Design Package

Download the Altium design package and production files are here.

Additional Resources

Press Release - https://www.semtech.com/company/press/semtech-unveils-lora-corecell-reference-design-for-full-duplex-gateway-applications-enabling-lorawan-gateways-to-receive-and-transmit-data-simultaneously

LoRa Core SX1302 Homepage - https://www.semtech.com/products/wireless-rf/lora-core/sx1302

LoRa® Corecell Reference Design for Full Duplex Gateway Applications for U.S. 915MHz - - https://www.semtech.com/products/wireless-rf/lora-core/sx1302cfd915gw1h

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